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| 256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 0.3 1.0 Initial Draft Modification of IDD Current Modification of IDD3P & IDD3PS IDD3P / IDD3PS : 3mA / 2mA --> 5mA / 5mA Final revision History Draft Date Aug. 2004 Oct. 2004 Jan. 2005 Jul. 2005 Remark Preliminary Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Jul. 2005 1 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series DESCRIPTION The Hynix Low Power SDRAM(Mobile SDR) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix HY5S5B6ELF(P) is a 268,435,456bit CMOS Synchronous Dynamic Random Access Memory. It is organized as 4banks of 4,194,304x16. The Low Power SDRAM(Mobile SDR) provides for programmable options including CAS latency of 1, 2, or 3, READ or WRITE burst length of 1, 2, 4, 8, or full page, and the burst count sequence(sequential or interleave). And the Low Power SDRAM(Mobile SDR) also provides for special programmable options including Partial Array Self Refresh of a quarter bank, a half bank, 1bank, 2banks, or all banks. The Hynix HY5S5B6ELF(P) has the special Low Power function of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current consumption. Since an internal temperature sensor is implanted, it enables to automatically adjust refresh rate according to temperature without external EMRS command. A burst of Read or Write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst Read or Write command on any cycle(This pipelined design is not restricted by a 2N rule). Deep Power Down Mode is a additional operating mode for Low Power SDRAM(Mobile SDR). This mode can achieve maximum power reduction by removing power to the memory array within each SDRAM. By using this feature, the system can cut off alomost all DRAM power without adding the cost of a power switch and giving up mother-board powerline layout flexibility. FEATURES Standard SDRAM Protocol Programmable CAS latency of 1, 2 or 3 -25oC ~ 85oC Operation Package Type : 54ball, 0.8mm pitch FBGA (Lead Free, Lead) Internal 4bank operation Power Supply Voltage : VDD = 1.8V, VDDQ = 1.8V LVCMOS compatible I/O Interface Low Voltage interface to reduce I/O power Low Power Features PASR(Partial Array Self Refresh) Auto TCSR (Temperature Compensated Self Refresh) DS (Drive Strength) Deep Power Down Mode - HY5S5B6ELFP : Lead Free - HY5S5B6ELF : Lead - 256M SDRAM ORDERING INFORMATION Part Number HY5S5B6ELF-HE HY5S5B6ELF-SE HY5S5B6ELFP-HE HY5S5B6ELFP-SE Clock Frequency 133MHz 105MHz 133MHz 105MHz CAS Latency 3 3 3 3 4banks x 4Mb x 16 LVCMOS Lead Free Organization Interface 54Ball FBGA Lead Rev 1.0 / Jul. 2005 2 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series BALL DESCRIPTION 9 8 7 3 2 1 A B C D E F G H J 54 Ball FBGA 0.8mm Ball Pitch 1 VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 7 8 DQ0 DQ2 DQ4 DQ6 LDQM /RAS BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 /WE /CS A10 VDD A B C D E F G H J VDDQ VSSQ VDDQ VSSQ VDD /CAS BA0 A0 A3 < Top View > Rev 1.0 / Jul. 2005 3 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series BALL DESCRIPTION Ball Out F2 SYMBOL CLK TYPE INPUT DESCRIPTION Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will be one of the states among (deep) power down, suspend or self refresh Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details Data Mask : Controls output buffers in read mode and masks input data in write mode F3 CKE INPUT G9 G7,G8 H7, H8, J8, J7, J3, J2, H3, H2, H1, G1, G3, H9, G2 F8, F7, F9 F1, E8 A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 A9, E7, J9, A1, E3, J1 A7, B3, C7, D3, A3, B7, C3, D7 E2, G1 CS BA0, BA1 INPUT INPUT A0 ~ A12 INPUT RAS, CAS, WE UDQM, LDQM INPUT INPUT DQ0 ~ DQ15 I/O Data Input/Output : Multiplexed data input/output pin VDD/VSS VDDQ/VSSQ NC SUPPLY SUPPLY - Power supply for internal circuits Power supply for output buffers No connection Rev 1.0 / Jul. 2005 4 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 16 I/O Mobile Synchronous DRAM PASR Extended Mode Register Self refresh logic & timer Internal Row Counter CLK CKE CS RAS CAS WE U/LDQM 4Mx16 Bank 3 Row Active State Machine Row Pre Decoder 4Mx16 Bank 2 4Mx16 Bank 1 4Mx16 Bank 0 Row decoders Row decoders Row decoders DQ0 Sense AMP & I/O Gate Row decoders I/O Buffer & Logic Refresh Memory Cell Array Column Active Column Pre Decoder Column decoders DQ15 Bank Select Column Add Counter A0 A1 Address Register Burst Length Burst Counter Address Buffers A12 BA1 BA0 Mode Register CAS Latency Data Out Control Rev 1.0 / Jul. 2005 5 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 0 BA0 0 A12 0 A11 0 A10 0 A9 OP Code A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 A0 CAS Latency Burst Length OP Code A9 0 1 Write Mode Burst Read and Burst Write Burst Read and Single Write Burst Type A3 0 1 Burst Type Sequential Interleave CAS Latency A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved 1 2 3 Reserved Reserved Reserved Reserved Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Burst Length A3 = 0 1 2 4 8 Reserved Reserved Reserved Full page A3=1 1 2 4 8 Reserved Reserved Reserved Reserved Rev 1.0 / Jul. 2005 6 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series BASIC FUNCTIONAL DESCRIPTION (Continued) Extended Mode Register BA1 1 BA0 0 A12 0 A11 0 A10 0 A9 0 A8 0 A7 0 A6 DS A5 A4 0 A3 0 A2 A1 PASR A0 DS (Driver Strength) A6 0 0 1 1 A5 0 1 0 1 Driver Strength Full 1/2 Strength 1/4 Strength Reserved PASR (Partial Array Self Refresh) A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Self Refresh Coverage All Banks Half of Total Bank (BA1=0 or Bank 0,1) Quarter of Total Bank (BA1=BA0=0 or Bank 0) Reserved Reserved Half of Bank 0(Bank 0 and Row Address MSB=0) Quarter of Bank 0(Bank 0 and Row Address 2 MSBs=0) Reserved Rev 1.0 / Jul. 2005 7 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series Power Up and Initialization Like a Synchronous DRAM, Mobile SDRAM must be powered up and initialized in a predefined manner. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined. Power applied VDD before or at the same time as VDDQ. After power up, an initial pause of 200 usec is required. And a precharge all command will be issued to the Mobile SDRAM. Then, 8 or more Auto refresh cycles will be provided. After the Auto refresh cycles are completed, a mode register set(MRS) command will be issued to program the specific mode of operation (Cas Latency, Burst length, etc.) And a extended mode register set command will be issued to program specific mode of self refresh operation(PASR). The following these cycles, the Mobile SDRAM is ready for normal opeartion. VDD VDDQ T=200usec tCK tRP 8*tRFC tMRD CLK LVCMOS High Level CKE Programming the registers Mode Register The mode register contains the specific mode of operation of the Mobile SDRAM. This register includes the selection of a burst length(1, 2, 4, 8, Full Page), a cas latency(1, 2 or 3), a burst type. The mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. Extended Mode Register The extended mode register contains the specific features of self refresh opeartion of the Mobile SDRAM. This register includes the selection of partial arrays to be refreshed(half array, quarter array, etc.). The extended mode register set must be done before any activate command after the power up sequence. Any contents of the mode register be altered by re-programming the mode register through the execution of extended mode register set command. Bank(Row) Active The Bank Active command is used to activate a row in a specified bank of the device. This command is initiated by activating CS, RAS and deasserting CAS, WE at the positive edge of the clock. The value on the BA1 and BA0 selects the bank, and the value on the A0-A12 selects the row. This row remains active for column access until a precharge command is issued to that bank. Read and write operations can only be initiated on this activated bank after the minimum tRCD time is passed from the activate command. Read The READ command is used to initiate the burst read of data. This command is initiated by activating CS, CAS, and deasserting WE, RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the READ burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. The length of burst and the CAS latency will be determined by the values programmed during the MRS command. Rev 1.0 / Jul. 2005 8 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series Write The WRITE command is used to initiate the burst write of data. This command is initiated by activating CS, CAS, WE and deasserting RAS at the positive edge of the clock. BA1 and BA0 inputs select the bank, A8-A0 address inputs select the starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected the row being accessed will be precharged at the end of the WRITE burst; if Auto Precharge is not selected, the row will remain active for subsequent accesses. Precharge The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If A10 is low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time is met after the precharge command is issued. Auto Precharge The Auto Precharge command is issued to close the open row in a particular bank after READ or WRITE operation. If A10 is high when a READ or WRITE command is issued, the READ or WRITE with Auto Precharge is initiated. Burst Termination The Burst Termination is used to terminate the burst operation. This function can be accomplished by asserting a Burst Stop command or a Precharge command during a burst READ or WRITE operation. The Precharge command interrupts a burst cycle and close the active bank, and the Burst Stop command terminates the existing burst operation leave the bank open. Data Mask The Data Mask comamnd is used to mask READ or WRITE data. During a READ operation, When this command is issued, data outputs are disabled and become high impedance after two clock delay. During a WRITE operation, When this command is issued, data inputs can't be written with no clock delay. CLK Command RD Masked by CKE CKE Internal CLK Frozen Int. CLK by CKE (CKE = Fixed Low) DQ Q1 Q2 Clock Suspend Mode Q3 Q4 Command CKE Internal CLK WR Masked by CKE Frozen Int. CLK by CKE (CKE = Fixed Low) DQ D1 D2 D3 Clock Suspend Mode D4 Rev 1.0 / Jul. 2005 9 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series Clock Suspend The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the device. During normal access mode, CKE is keeping High. When CKE is low, it freezes the internal clock and extends data Read and Write operations. (See examples in next Figures) Power Down The Power Down command is used to reduce standby current. Before this command is issued, all banks must be precharged and tRP must be passed after a precharge command. Once the Power Down command is initiated by keeping CKE low, all of the input buffer except CKE are gated off. Auto Refresh The Auto Refresh command is used during normal operation and is similar to CBR refresh in Coventional DRAMs. This command must be issued each time a refresh is required. When an Auto Refresh command is issued , the address bits is ''Don't care'', because the specific address bits is generated by internal refresh address counter. Self Refresh The Self Refresh command is used to retain cell data in the Mobile SDRAM. In the Self Refresh mode, the Mobile SDRAM operates refresh cycle asynchronously. The Self Refresh command is initiated like an Auto Refresh command except CKE is disabled(Low). The Mobile SDRAM can accomplish an special Self Refresh operation by the specific modes(PASR) programmed in extended mode registers. The Mobile SDRAM can control the refresh rate automatically by the temperature value of Auto TCSR(Temperature Compensated Self Refresh) to reduce self refresh current and select the memory array to be refreshed by the value of PASR(Partial Array Self Refresh). The Mobile SDRAM can reduce the self refresh current(IDD6) by using these two modes. Deep Power Down The Deep Power Down Mode is used to achieve maximum power reduction by cutting the power of the whole memory array of the devices. For more information, see the special operation for Low Power consumption of this data sheet. Rev 1.0 / Jul. 2005 10 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series COMMAND TRUTH TABLE Function Mode Register Set Extended Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop Data Write/Output Enable Data Mask/Output Disable Auto Refresh Self Refresh Entry Self Refresh Exit Precharge Power Down Entry Precharge Power Down Exit Clock Suspend Entry Clock Suspend Exit Deep Power Down Entry Deep Power Down Exit CKEn-1 H H H H H H H H H H H H H H H H L H L H L H L CKEn X X X X X X X X X X X X X X H L H L H L H L H CS L L L H L L L L L L L L RAS L L H X L H H H H L L H X X CAS L L H X H L L L L H H H WE L L H X H H H L L L L L DQM X X X X X X X X X X X X V ADDR A10 /AP BA Note 2 2 Op Code Op Code X X Row Address Column Column Column Column X X L H L H H L X X X X X X X X X X X X V V V V V X V L L H L H L H L H L L L L X H X H X H X V X H X L L X H X H X H X V H H H X H X H X H X V L X X X X X X X X X 1 Note : 1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high. 2. BA1/BA0 must be issued 0/0 in the mode register set, and 1/0 in the extended mode register set. Rev 1.0 / Jul. 2005 11 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CURRENT STATE TRUTH TABLE (Sheet 1 of 4) Current State Command CS RAS CAS WE L L L L idle L L L H L L L L Row Active L L L H L L L Read L L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 A11-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set Action Set the Mode Register Notes 14 5 Auto or Self Refresh Start Auto or Self Refresh Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation Activate the specified bank and row ILLEGAL ILLEGAL No Operation No Operation or Power Down ILLEGAL 4 4 3 3 13,14 13 7 4 6 6 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Precharge ILLEGAL Start Write : optional AP(A10=H) Start Read : optional AP(A10=H) No Operation No Operation ILLEGAL 13,14 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst 4 8,9 8 Rev 1.0 / Jul. 2005 12 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CURRENT STATE TRUTH TABLE (Sheet 2 of 4) Current State Read Command CS RAS CAS WE H L L L L Write L L L H L L L Read with Auto Precharge L L L L H L L Write with Auto Precharge L L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X A11-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action Continue the Burst ILLEGAL 13,14 13 10 4 8 8,9 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set Termination Burst: Start the Precharge ILLEGAL Termination Burst: Start Write(optional AP) Termination Burst: Start Read(optional AP) Continue the Burst Continue the Burst ILLEGAL 13,14 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst ILLEGAL 13,14 13 4,12 4,12 12 12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue the Burst Continue the Burst Rev 1.0 / Jul. 2005 13 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CURRENT STATE TRUTH TABLE (Sheet 3 of 4) Current State Command CS RAS CAS WE L L L L Precharging L L L H L L L L Row Activating L L L H L L L L Write Recovering L L L L L L L H H H X L L L L H H H X L L L L H H H L L H H L L H X L L H H L L H X L L H H L L H L H L H L H H X L H L H L H H X L H L H L H H X BA BA BA BA X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 A11-A0 OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X Description Mode Register Set ILLEGAL Action Notes 13,14 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set No Operation: Bank(s) idle after tRP ILLEGAL ILLEGAL ILLEGAL No Operation: Bank(s) idle after tRP No Operation: Bank(s) idle after tRP ILLEGAL 4,12 4,12 4,12 13,14 13 4,12 4,11,1 2 4,12 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Row Active after tRCD No Operation: Row Active after tRCD ILLEGAL 13,14 13 4,13 4,12 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation ILLEGAL ILLEGAL Start Write: Optional AP(A10=H) Start Read: Optional AP(A10=H) No Operation: Row Active after tDPL 9 Rev 1.0 / Jul. 2005 14 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CURRENT STATE TRUTH TABLE (Sheet 4 of 4) Current State Write Recovering Command CS RAS CAS WE H L L L Write Recovering with Auto Precharge L L L L H L L L L Refreshing L L L H L L L Mode Register Accessing L L L L H X L L L L H H H X L L L L H H H X L L L L H H H X X L L H H L L H X L L H H L L H X L L H H L L H X X L H L H L H H X L H L H L H H X L H L H L H H X X BA BA BA BA X X X BA BA BA BA X X X BA BA BA BA X X BA0/ BA1 X A11-A0 X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X OP CODE X X Row Add. Col Add. A10 Col Add. A10 X X Description Device Deselect Mode Register Set Action No Operation: Row Active after tDPL ILLEGAL 13,14 13 4,13 4,12 4,12 4,9,12 Notes Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: Precharge after tDPL No Operation: Precharge after tDPL ILLEGAL 13,14 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect Mode Register Set ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after tRC No Operation: idle after tRC ILLEGAL 13,14 13 13 13 13 13 Auto or Self Refresh ILLEGAL Precharge Bank Activate Write/WriteAP Read/ReadAP No Operation Device Deselect ILLEGAL ILLEGAL ILLEGAL ILLEGAL No Operation: idle after 2 clock cycles No Operation: idle after 2 clock cycles Rev 1.0 / Jul. 2005 15 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series Note : 1. H: Logic High, L: Logic Low, X: Don't care, BA: Bank Address, AP: Auto Precharge. 2. All entries assume that CKE was active during the preceding clock cycle. 3. If both banks are idle and CKE is inactive, then in power down cycle 4. Illegal to bank in specified states. Function may be legal in the bank indicated by Bank Address, depending on the state of that bank. 5. If both banks are idle and CKE is inactive, then Self Refresh mode. 6. Illegal if tRCD is not satisfied. 7. Illegal if tRAS is not satisfied. 8. Must satisfy burst interrupt condition. 9. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. Must mask preceding data which don't satisfy tDPL. 11. Illegal if tRRD is not satisfied 12. Illegal for single bank, but legal for other banks in multi-bank devices. 13. Illegal for all banks. 14. Mode Register Set and Extended Mode Register Set is same command truth table except BA1. Rev 1.0 / Jul. 2005 16 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 1) Current State CKE Previous Current Cycle Cycle H L L L L L L H L Power Down L H L X H H H H H L X H CS X H L L L L X X H L RAS X X H H H L X X X H L X X L H Deep Power Down L L L X H L X X X X X X X X Command CAS X X H H L X X X X H X L X X X X X WE X X H L X X X X X H X X L X X X X BA0, BA1 X X X X X X X X X X X X X X X X X A11A0 X X X X X X X X X X X X X X X X X Maintain Power Down Mode INVALID Deep Power Down mode exit Maintain Deep Power Down Mode 1 5 ILLEGAL 2 INVALID Exit Self Refresh with Device Deselect Exit Self Refresh with No Operation ILLEGAL ILLEGAL ILLEGAL Maintain Self Refresh INVALID Power Down mode exit, all banks idle 1 2 Action Notes 1 2 2 2 2 2 Self Refresh Rev 1.0 / Jul. 2005 17 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CKE Enable(CKE) Truth TABLE (Sheet 2 of 2) Current State CKE Previous Current Cycle Cycle H H H H All Banks Idle H H H H H H L H Any State other than listed above H H H H H L L L L L X H CS H L L L L H L L L L X X RAS X H L L L X H L L L X X Command CAS X X H L L X X H L L X X WE X X X H L X X X H L X X X X X X BA0, BA1 A11A0 Action Notes 3 3 3 Refer to the idle State section of the Current State Truth Table Auto Refresh Mode Register Set Refer to the idle State section of the Current State Truth Table Entry Self Refresh Mode Register Set Power Down Refer to operations of the Current State Truth Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend OP CODE 4 3 3 3 4 OP CODE X X X X 4 H L L L H L X X X X X X X X X X X X X X X X X X Note : 1. For the given current state CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high. 3. The address inputs depend on the command that is issued. 4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered from the all banks idle state. 5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high and is maintained for a minimum 200usec. Rev 1.0 / Jul. 2005 18 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time Symbol TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER Rating -25 ~ 85 -55 ~ 125 -1.0 ~ 2.6 -1.0 ~ 2.6 -1.0 ~ 2.6 50 1 260 . 10 Unit oC oC V V V mA W oC . Sec DC OPERATING CONDITION (TA= -25 to 85oC ) Parameter Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Symbol VDD VDDQ VIH VIL Min 1.70 1.70 0.8*VDDQ -0.3 Typ 1.8 1.8 Max 1.95 1.95 VDDQ+0.3 0.3 Unit V V V V Note 1 1, 2 1, 2 1, 2 - Note : 1. All Voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD AC OPERATING TEST CONDITION (TA= -25 to 85 oC, VDD = 1.8V, VSS = 0V) Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Note 1. Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 0.9*VDDQ/0.2 0.5*VDDQ 1 0.5*VDDQ 30 Unit V V ns V pF Note 1 Vtt=0.5xVDDQ 50 Output ZO=50 30pF Rev 1.0 / Jul. 2005 19 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series CAPACITANCE (TA= 25 oC, f=1MHz) Parameter Pin CLK Input capacitance Data input/output capacitance A0~A12, BA0, BA1, CKE, CS, RAS, CAS, WE, UDQM, LDQM DQ0 ~ DQ15 Symbol CI1 CI2 CI/O H/S Min 2 2 3.5 Max 4.0 4.0 6.0 Unit pF pF pF DC CHARACTERRISTICS I (TA= -25 to 85oC) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1. VIN = 0 to 1.8V. All other pins are not tested under VIN=0V. 2. DOUT is disabled. VOUT= 0 to 1.95V. 3. IOUT = - 0.1mA 4. IOUT = + 0.1mA Symbol ILI ILO VOH VOL Min -1 -1 VDDQ-0.2 - Max 1 1 0.2 Unit uA uA V V Note 1 2 3 4 Rev 1.0 / Jul. 2005 20 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series DC CHARACTERISTICS II (TA= -25 to 85oC) Parameter Symbol Test Condition Burst length=1, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. CKE VIL(max), tCK = 15ns CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V CKE VIH(min), tCK = Input signals are stable. tCK tCK(min), IOL=0mA All banks active tRFC tRFC(min), CKE 0.2V See p.26~27 100 95 See Next Page Speed H 60 0.5 0.35 S 50 Unit Note Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS mA mA mA 1 Precharge Standby Current in Non Power Down Mode IDD2N 15 mA 7 5 5 IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS mA Active Standby Current in Non Power Down Mode IDD3N 20 mA 20 75 mA mA mA uA 2 1 IDD3NS Burst Mode Operating Current Auto Refresh Current Self Refresh Current Standby Current in Deep Power Down Mode Note : IDD4 IDD5 IDD6 IDD7 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. See the tables of next page for more specific IDD6 current values. Rev 1.0 / Jul. 2005 21 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series DC CHARACTERISTICS III - Low Power (IDD6) Temp. ( oC) 45 85 Memory Array 4 Banks 300 450 2 Banks 240 320 1 Bank 200 270 Unit uA uA Rev 1.0 / Jul. 2005 22 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter System Clock Cycle Time Clock High Pulse Width Clock Low Pulse Width Access Time From Clock Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z Time CLK to Data Output in High-Z Time CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 CAS Latency=3 CAS Latency=2 Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 H Min 7.5 12 3.0 3.0 2.0 2.0 1.0 2.0 1.0 2.0 1.0 2.0 1.0 1.0 Max 1000 1000 6.5 9.0 6.5 9.0 Min 9.5 15 3.5 3.5 2.0 3.0 1.5 3.0 1.5 3.0 1.5 3.0 1.5 1.0 S Max 1000 1000 7.0 10 7.0 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 1 1 2 2 Note Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev 1.0 / Jul. 2005 23 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay AUTO REFRESH Period CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In to Active Command DQM to Data-Out Hi-Z DQM to Data-In Mask MRS to New Command Precharge to Data Output High-Z Power Down Exit Time Self Refresh Exit Time Refresh Time CAS Latency=3 CAS Latency=2 Symbol tRC tRCD tRAS tRP tRRD tRFC tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF 2 0 2 3 2 1 1 H Min 72.5 22.5 50 22.5 15 80 1 0 2 Max 100K Min 90 28.5 60 28.5 19 80 1 0 2 S Max 100K Unit Note ns ns ns ns ns ns CLK CLK CLK tDPL+tRP 64 2 0 2 3 2 1 1 64 CLK CLK CLK CLK CLK CLK CLK ms 1 Note : 1. A new command can be given tRC after self refresh exit. Rev 1.0 / Jul. 2005 24 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series Special Operation for Low Power Consumption Deep Power Down Mode Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. Full initialization is required when the device exits from Deep Power Down Mode. Truth Table Current State Idle Deep Power Down Command Deep Power Down Entry Deep Power Down Exit CKEn-1 H L CKEn L H CS L X RAS H X CAS H X WE L X Deep Power Down Mode Entry The Deep Power Down Mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of the clock, while CKE is low. The following diagram illustrates deep power down mode entry. CLK CKE CS RAS CAS WE tRP Precharge if needed Rev 1.0 / Jul. 2005 Deep Power Down Entry 25 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions for a minimum of 200usec 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands 4. Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register The following timing diagram illustrates deep power down mode exit sequence. CLK CKE CS RAS CAS WE 200s tRP tRC Deep Power Down exit All Banks Precharge Auto refresh Auto refresh Mode Register Set Extended Mode Register Set New Command Accepted Here Rev 1.0 / Jul. 2005 26 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6ELF(P)-xE Series PACKAGE INFORMATION 54 Ball FBGA 0.8mm pitch (Size 8.0mm x 12.0mm) 8.00 Typ. 3.20 1.60 0.80 A1 INDEX MARK Unit [mm] 0.80 Typ. 12.00 Typ. Bottom View 0.40 0.45 +/- 0.05 0.34 +/- 0.05 2.80 1.375 0.80 Typ. 1.00 max Rev 1.0 / Jul. 2005 27 |
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